Scalable gate and storage dielectric

ABSTRACT

Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

BACKGROUND OF THE INVENTION

[0001] This invention relates to gate and storage dielectrics ofintegrated circuit devices. More particularly, this invention relates toscalable gate and storage dielectric systems.

[0002] A dielectric is an insulating material capable of storingelectric charge and associated energy by means of a shift in therelative positions of internally bound positive and negative chargesknown as charge dipoles. This shift is brought about by an externalelectric field. A dielectric system is a collaborating arrangement ofmaterials including at least one dielectric material.

[0003] Dielectric systems are directly involved in the progress ofmicroelectronic process technology. Successes in the manufacture ofquality dielectric systems have done much to advance integrated circuittechnology. Improved dielectric systems have traditionally resulted insignificant increases in electronic device and system capabilities.

[0004] The quality of a dielectric system can be determined generally bya well-defined criteria. One criterion is the effective dielectricconstant K of the system. The effective dielectric constant is dependenton the individual dielectric constants of the materials used in thesystem. A dielectric constant indicates the relative capacity, ascompared to a vacuum where K=1, of the material to store charge. Thus,high dielectric constant materials advantageously produce dielectricsystems with high capacity to store charge.

[0005] Another criterion is the scalability of the system. Scalabilityof a dielectric system refers to its physical size (i.e., its thickness,measured in nanometers, and area). In particular, the ability tominimize the size of the system is important. Note that a system'sthickness and area can each be scaled independently of the other. Adielectric system having a geometrically scalable thickness may allowhigher charge storage capacity. A dielectric system having ageometrically scalable area may allow more transistors to be fabricatedon a single integrated circuit chip, thus allowing increasedfunctionality of that chip.

[0006] Additional criteria for determining the quality of a dielectricsystem are dielectric interface compatibility and high temperaturestructural stability. In order to produce a stable and reliable device,a dielectric must be chemically compatible with the semiconductorsubstrate or plate material with which the dielectric forms aninterface. The substrate or plate material is usually silicon. Inaddition, the substrate and dielectric interface must remain stable overa range of temperatures.

[0007] Other criteria are a dielectric system's ability to providecharge control and stoichiometric reproducibility at asubstrate/dielectric or plate/dielectric interface. Uncontrollablebonding at an interface may decrease device reliability and causeinconsistent device characteristics from one device to another. Danglingatoms (i.e., atoms that have not formed bonds) from the dielectricmaterial may contribute to an undesirable charge accumulation at theinterface. Charge accumulation varying from device to device can lead toan undesirably varying threshold voltage from device to device. Thethreshold voltage can be defined as the minimum voltage applied to agate electrode of a device that places the device in active mode ofoperation.

[0008] In addition, leakage characteristics of a dielectric material areparticularly important when the dielectric material is used in scaleddown devices. A thin gate dielectric often gives rise to an undesirabletunneling current between a gate and the substrate. Tunneling currentresults in wasted power and is particularly destructive in memorycircuitry, in which capacitors coupled to a gate dielectric system maybe undesirably discharged by the tunneling (i.e., leakage) current.

[0009] High temperature chemical passivity is also an importantcriterion of a dielectric system. A gate dopant may undesirably diffusethrough a gate dielectric material during high temperature devicefabrication, corrupting the substrate/dielectric or plate/dielectricinterface. The dopant may form bonds with the dielectric material andthe substrate or plate material causing an undesirable negative chargebuildup at the interface. This negative charge may also result in anundesirable increase in the threshold voltage of the device.

[0010] Further, the quality of a dielectric system is also determined byits breakdown characteristics. A uniform dielectric breakdowncharacteristic across multiple dielectric systems is advantageousbecause breakdown of a single dielectric system in a device or circuitcan cause undesirable and unpredictable device or circuit operation.Loosely defined, a dielectric breakdown occurs when a voltage applied toa dielectric system exceeds a breakdown voltage limit of the dielectricmaterial as it is arranged in the system. Moreover, the breakdown of astorage dielectric can cause stored charge to undesirably dissipate.Thus, a uniform dielectric breakdown characteristic increases systemfunctionality, reliability, and robustness.

[0011] Finally, the quality of a dielectric system is further determinedby its ability to permit etch selectivity during fabrication. Etchselectivity refers to an ability to selectively remove material to leavebehind a desired pattern. The desired pattern corresponds to thearrangement of materials in a system or device. A material that is notsignificantly etch selective may pose problems in the fabrication ofthat system or device, as the material may not permit structuralintegration with other materials of the device.

[0012] In an ongoing effort to develop improved dielectric systems,diligent research and experimentation have highlighted problematicdielectric system characteristics. Known limitations of traditionaldielectric material silicon dioxide (SiO₂), namely its low K value, highleakage characteristic resulting from increased scaling, and its hightemperature chemical impassivity, show the need for improved dielectricmaterials and systems. Attempts to find improved dielectric materialsand systems, as defined by the criteria described above, have hadlimited success. Particularly, attempts to develop a dielectric systemthat concurrently satisfies all of the above concerns and issues andthat overcomes the limitations of SiO₂ have been unsuccessful.

[0013] In view of the foregoing, it would be desirable to provideimproved dielectric systems.

[0014] It would also be desirable to provide methods of fabricatingimproved dielectric systems.

SUMMARY OF THE INVENTION

[0015] It is an object of the present invention to provide improveddielectric systems.

[0016] It is also an object of the present invention to provide methodsof fabricating improved dielectric systems.

[0017] Gate and storage dielectric systems of the present inventionprovide high effective K values. Improved gate and storage dielectricstacks include a high K dielectric material that produces improveddevice characteristics such as increased storage capacity and increaseddrive current. Additionally, the improved dielectric stacks include apassivated overlayer that maintains the high effective K values, is inaddition to other desirable characteristics. For example, asilicon-rich-nitride passivated overlayer advantageously provides astoichiometric interface between a dielectric and a substrate or storageplate. In addition, a silicon-rich-nitride passivated overlayeradvantageously provides charge control and regulation of thresholdvoltage in metal-oxide-semiconductor field effect transistors (MOSFETs).

[0018] Methods of fabricating improved gate and storage dielectricsystems are also provided by the present invention. A substrate orbottom storage plate is carefully prepared before subsequent depositionof metal or, in other embodiments, dielectric material. Metal ordielectric materials are deposited to minimize thickness and to maximizestorage capacity. Increased storage capacity, which is alsocharacteristic of high K materials, increases area scaling capabilities.Increased area scaling can reduce the integrated circuit chip arearequired to fabricate an integrated circuit device. Thus, either moredevices can be fabricated on a single integrated circuit chip,advantageously allowing increased functionality, or more integratedcircuit chips can be fabricated on a single wafer, advantageouslyreducing costs.

[0019] The passivated overlayer is deposited such that the resulting Kvalue of the overlayer does not compromise the high K value of thedielectric used in the dielectric stack. Dielectric stacks may beappropriately annealed to provide greater stack stability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects and advantages of the invention willbe apparent upon consideration of the following detailed description,taken in conjunction with the accompanying drawings, in which likereference characters refer to like parts throughout, and in which:

[0021]FIG. 1 is a cross-sectional diagram of an exemplary embodiment ofa gate dielectric stack according to the invention;

[0022]FIG. 2 is a cross-sectional diagram of a known gate dielectricstack;

[0023]FIG. 3 is a graph of dielectric constants versus refractiveindices of silicon-rich-nitride;

[0024]FIG. 4 is a cross-sectional diagram of an exemplary embodiment ofa storage dielectric stack according to the invention;

[0025]FIGS. 5 and 6 are cross-sectional diagrams of improved integratedcircuit devices using the dielectric stacks of the invention;

[0026]FIG. 7 is a flowchart of an exemplary embodiment of a method offabricating a dielectric stack according to the invention;

[0027]FIG. 8 is a graph of refractive indices of silicon-rich-nitrideversus ratios of dichlorosilane-to-ammonia used in the fabrication ofsilicon-rich-nitride; and

[0028]FIG. 9 is a flowchart of another exemplary embodiment of a methodof fabricating a dielectric stack according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention provides improved dielectric systems andmethods of their fabrication in which many quality concerns and issuesof dielectric systems are preferably concurrently satisfied.

[0030]FIG. 1 shows a gate dielectric stack 100 in accordance with theinvention. Stack 100 includes substrate 102, gate dielectric 104,passivated overlayer 106, gate 108, and gate electrode 110. Substrate102 can be one or more semiconductor layers or structures which caninclude active or operable portions of semiconductor devices. Generally,substrate 102 comprises silicon (Si). Gate 108 can comprise a degenerateheavily doped polysilicon, a metal, or other conductive material.

[0031] Gate dielectric 104, which can also be referred to as gateinsulator 104, includes a single phasestoichiometrically-uniform-composition material having a high dielectricconstant (e.g., K≧10) or a silicon or transition-metal doped derivativethereof. A single phase stoichiometrically uniform material includes asingle material having a consistently precise number of atoms and bondsin a molecule of the material. A transition metal dopant of gatedielectric 104 may be zirconium, tungsten, hafnium, titanium, tantalum,or other suitable transition metal. In particular, gate dielectric 104is preferably stoichiometric alumina (Al₂O₃), which has a K value in therange of about 11 to about 12. Alumina is oxidized aluminum, a metalwhich can be deposited one atomic layer at a time to form ultra thinmetal films (e.g., less than about 3 nm). These metal films aresubsequently oxidized in ultra pure oxygen or ozone plasma to producestoichiometric alumina. Alternatively, gate dielectric 104 can be acomposite such as silicon-doped alumina or transition-metal-dopedalumina, each typically having a K>15.

[0032] A high K dielectric permits greater scalability of a dielectricstack. Scalability of a dielectric stack refers to the ability to reducethe size of the stack. Smaller dielectric stacks preferably allow, amongother things, more transistors to be fabricated on an integrated circuitchip, thus allowing more functionality on that chip. Greater scalabilityof the area occupied by the stack is possible because a high K gatedielectric has a higher dielectric capacitance per unit area (C_(d)) fora fixed dielectric thickness (t_(d)) than a lower K dielectric material,such as traditionally used silicon dioxide (K≈4). This is shown in therelationship C_(d)∝K/t_(d). A higher dielectric capacitance per unitarea corresponds to a higher capacity to store charge, which cancompensate for the storage capacity characteristically lost when thearea of a dielectric device or system is scaled.

[0033] Moreover, because drive current is directly proportional todielectric capacitance in metal-oxide-semiconductor field effecttransistors (MOSFETs), the increased dielectric capacitance per unitarea provided by a high K dielectric provides increased drive current.Drive current can be generally defined as the current flowing throughinduced channel 118 from drain electrode 120 to source electrode 122when, in the presence of sufficient potential between drain electrode120 and source electrode 122, a voltage equal to or greater than thethreshold voltage of the MOSFET device is applied to the gate. A low Kdielectric material in gate dielectric 104 may not provide sufficientdrive current, even when the thickness of gate dielectric 104 is scaled.Thus, to provide sufficient drive current, a high K dielectric is oftenrequired.

[0034] The scalability of high K gate dielectric 104 is but oneconsideration when evaluating the quality of a dielectric system.Because gate dielectric 104 forms interface 112 with substrate 102, thegate dielectric material should also be chemically compatible with thesubstrate material.

[0035] Alumina, when used as gate dielectric 104, is chemicallycompatible with a silicon substrate 102. However, the combination of thetwo materials does not inherently provide a stoichiometric interface atinterface 112. During device fabrication, hydroxide ions can causeundesirable and nonstoichiometric formation of alumino-silicate(Al_(x)Si_(y)O_(z)) at interface 112. The hydroxide ions may be absorbedinto a silicon substrate or plate in the form of Si_(x)O_(y)H_(z) andmay be naturally present due to exposure of the substrate or plate toopen air or to ambient hydroxide. Alumino-silicate formed at interface112 can have an undesirably lower K value than the stoichiometricalumina gate dielectric, producing an undesirably lower effective Kvalue for the dielectric stack. Moreover, known fabrication methods mayresult in uncontrollable and incomplete alumino-silicate bonding atinterface 112.

[0036] Incomplete bonding at interface 112 can cause an undesirableaccumulation of fixed negative charge at interface 112. This may resultin an undesirable increase in the threshold voltage of the device. Inparticular, dangling atoms from the dielectric material of gatedielectric 104 (i.e., atoms that have not formed bonds) and fromsubstrate 102 may contribute to the undesirable fixed interface chargeaccumulation at interface 112.

[0037] Passivated overlayer 106 advantageously prevents dopant used ingate 108 from readily diffusing through high K gate dielectric 104 toform bonds at interface 112. This dopant diffusion phenomenon may beespecially evident at high temperatures common during devicefabrication. For example, as shown in FIG. 2, the combination of aphosphorus-doped silicon gate 208 deposited directly upon alumina gatedielectric 204 causes the formation of an alumino-phospho-silicate layer203 at interface 212. Interface 212 may have originally been less of anuncorrupted interface between gate dielectric 204 and silicon substrate202 before high temperature fabrication caused phosphorous dopantdiffusion through gate dielectric 204.

[0038] Alumino-phospho-silicate layer 203 may contribute to negativecharge buildup (Q_(I)) at interface 212. The known device of FIG. 2generally has a fixed Q_(I)≈3e+13 (i.e., Q_(I)≈3×10¹³) fundamentalcharge units per cm². One fundamental charge unit is equal to about1.60218e−19 coulombs. As described above, a fixed charge accumulation inthe dielectric material undesirably causes an increase in the thresholdvoltage. Because dopant diffusion through gate dielectric 204 may beuncontrollable, formation of alumino-phospho-silicate layer 203 may beuncontrollable. Consequently, the negative charge at interface 212, andthe threshold voltage of any device that uses this known stack, may beuncontrollable and may undesirably vary from device to device.

[0039] Alumino-phospho-silicate layer 203 may also have a lower K valuethan that of gate dielectric 204. This causes an undesirable lowering ofthe effective K value of the dielectric stack. Again, this wouldadversely affect at least one of the advantages of having a high Kvalue, namely scalability.

[0040] Returning to FIG. 1, passivated overlayer 106 forms chemicallyinert interface 114 with gate 108 and forms chemically inert interface116 with gate dielectric 104. A chemically inert interface is aninterface at which no substantial bonding occurs between the materialsforming the interface.

[0041] Passivated overlayer 106 preferably provides high temperaturechemical passivity in dielectric stack 100. In particular, passivatedoverlayer 106 prevents diffusion of dopant from gate 108 through gatedielectric 104, which would subsequently corrupt interface 112 and lowerthe effective K value of the stack. Passivated overlayer 106 thusprevents additional fixed charge formation. Consequently, thecombination of the contaminant protection of passivated overlayer 106and the stoichiometry of interface 112 provides a reduced interfacecharge in the device of FIG. 1. Stack 100 advantageously has a fixedQ_(I) approximately ≦3e+10 fundamental charge units per cm², which issignificantly less than the typical fixed interface charge of knowndevices of Q_(I)≈3e+13 fundamental charge units per cm².

[0042] In addition, passivated overlayer 106 preferably providesuniformity in the dielectric breakdown voltage limit of the dielectricstack. The contaminant protection provided by passivated overlayer 106prevents local (i.e., geometrically small) defects in gate dielectric104 that contribute to a lower dielectric breakdown voltage. Moreover,in the absence of passivated overlayer 106, uncontrollable dopantdiffusion into gate dielectric 104 may likely result in an undesirablyuncontrollable and varying threshold voltage.

[0043] Further, passivated overlayer 106 preferably provides uniforminjection of either electrons or holes from gate 108 into gatedielectric 104 when a voltage is applied to gate electrode 110. Theinjection of electrons or holes corresponds respectively to either ann-type or p-type gate 108. Passivated overlayer 106 thus improvesreliability and uniformity in gate dielectric stack 100.

[0044] Passivated overlayer 106 is preferably “injector”silicon-rich-nitride (SRN), which is an SRN with a refractive index ofabout 2.5 or greater, and preferably has a thickness in the range ofabout 0.5 to about 3.0 nm. Injector SRN can be characterized as a twophase insulator consisting of uniformly distributed silicon nanocrystals in a body of stoichiometric nitride. A refractive index ofabout 2.5 or greater provides passivated overlayer 106 with a dielectricconstant comparable to or greater than that of a high K gate dielectric104. Particularly, injector SRN has a dielectric constant that isgreater than or equal to 12, which is the K value of silicon. Thus, thebenefits of a high K gate dielectric 104, as described above, are notcanceled by the addition of passivated overlayer 106. Alternatively,passivated overlayer 106 can be an SRN with a refractive index of lessthan about 2.5; however, a maximum K and the benefits associatedtherewith in a dielectric stack are achieved when the refractive indexis greater than about 2.5.

[0045]FIG. 3 illustrates the relationship between the refractive indicesand dielectric constants K of injector SRN. As shown, injector SRN witha refractive index of about 2.5 or greater provides a K value greaterthan about 12, which is the dielectric constant of silicon.

[0046]FIG. 4 shows a storage dielectric stack 400 in accordance with theinvention. Stack 400 includes bottom plate 402, storage dielectric 404,passivated overlayer 406, and top plate 408. Bottom plate 402 and topplate 408 can be a degenerate heavily doped silicon, a doped polysiliconmaterial, a metal, or other conductive material.

[0047] Storage dielectric 404 is preferably the same material as that ofgate dielectric 104, namely alumina or a doped derivative of alumina. Aspreviously described, alumina is oxidized aluminum, a metal which can bedeposited in ultra thin metal films (e.g., less than about 3 nm) andsubsequently oxidized in ultra pure oxygen or ozone plasma to producestoichiometric alumina. A high K dielectric value (e.g., K≧10) instorage dielectric 404 provides a higher storage capacity, which isadvantageous in memory devices such as DRAMs (dynamic random accessmemories). High storage capacity in high K dielectrics results from thehigh capacitance per unit area provided by high K dielectrics, aspreviously described.

[0048] Passivated overlayer 406 is preferably the same material as thatof passivated overlayer 106, namely injector SRN or SRN, and preferablyserves the same or similar purposes in the stack. In particular,passivated overlayer 406 prevents diffusion of dopant from top plate 408through storage dielectric 404. Passivated overlayer 406 providesuniform injection of electrons or holes from top plate 408 into storagedielectric 404 during voltage stress and provides uniform dielectricbreakdown in storage dielectric 404. Passivated overlayer 406 preferablyhas the same range of thickness (i.e., about 0.5 to about 3 nm) andrefractive index (i.e., ≧about 2.5) as passivated overlayer 106. Thefixed charge (Q_(I)) at interface 412 is advantageously about the sameas in gate dielectric stack 100, namely Q_(I) approximately <3e+10 unitsof fundamental charge per cm².

[0049]FIG. 5 shows an integrated circuit device 500 using the dielectricstacks of the invention. Device 500 is an embodiment of a deep trenchstorage capacitor DRAM cell that includes embodiments of the gate andstorage dielectric stacks of the invention. Storage (capacitor)dielectric stack 501 includes bottom plate/substrate 502, storagedielectric 504, passivated overlayer 506, and top plate 508. A logicdata bit is written into storage dielectric stack 501 via bit line 510when sufficient voltage is applied to bit line 510 and the voltage atword line 512 (i.e., at the gate electrode) rises above the thresholdvoltage of gate dielectric stack 100. Conversely, a logic data bit isread from storage dielectric stack 501 via bit line 510 wheninsufficient voltage is applied to bit line 510 and the voltage at wordline 512 rises above the threshold voltage of gate dielectric stack 100.Oxide 514, oxide 516, and oxide 518 isolate storage dielectric stack501. Improved device characteristics of device 500 are obtained fromgate dielectric stack 100 and storage dielectric stack 501. For example,stoichiometric interface 112 provides a desirable lower thresholdvoltage for performing both read and write operations. Also, theimproved charge storage capacity of storage dielectric stack 501enhances memory capacity and reliability.

[0050] Similarly, FIG. 6 shows another embodiment of an improved DRAMcapacitor device using the dielectric stacks of the invention. Device600 is a stacked capacitor DRAM cell that includes gate dielectric stack100 and storage (capacitor) dielectric stack 601 in accordance with theinvention. Storage dielectric stack 601 includes bottom plate 602,storage dielectric 604, passivated overlayer 606, and top plate 608.Operation of device 600 is similar to that of device 500. A logic databit is written into storage dielectric stack 601 via bit line 610 whensufficient voltage is applied to bit line 610 and the voltage at wordline 612 (i.e., at the gate electrode) rises above the threshold voltageof gate dielectric stack 100. Conversely, a logic data bit is read fromstorage dielectric stack 601 via bit line 610 when insufficient voltageis applied at bit line 610 and the voltage at word line 612 rises abovethe threshold voltage of gate dielectric stack 100. Current flowsthrough electrical contact 614 as storage dielectric stack 601 chargesand discharges. The improved characteristics of device 600 are similarto those of device 500 and are similarly obtained from the dielectricstacks of the invention.

[0051] The gate and storage dielectric stacks of FIGS. 1 and 4-6 can befabricated by the method shown in FIG. 7 in accordance with theinvention. Process 700 begins at 702 by first preparing the siliconsubstrate or silicon bottom plate of a dielectric stack. Native radicalhydroxide ions (OH⁻) are removed from at least a portion of the surfaceof, for example, silicon substrate 102 or silicon bottom plate 402.Hydroxide ions may be present in bonds of silicon and silicon hydroxide(Si_(x)O_(y)H_(z)) that can form naturally in silicon exposed to openair or to ambient hydroxide. If not removed, these radical hydroxideions may react with a metal-derived gate dielectric material andsubstrate material, or a metal-derived storage dielectric material andbottom plate material, to form nonstoichiometric bonding. For example,radical hydroxide ions may react with aluminum and silicon to form anonstoichiometric Al_(x)Si_(y)O_(z) material. The removal of OH⁻involves controllably introducing a hydrofluoric acid (HF) vapor in anultra pure nitrogen bleed-in, while maintaining sufficient vacuum.Generally, a vacuum of approximately less than about 10⁻⁶ torr issufficient and can be maintained in a high vacuum chamber.

[0052] Next, at 704, a single atomic layer of a metal is deposited onthe prepared substrate or bottom plate. The metal is preferablyaluminum, subsequently oxidized using a controlled amount of ultra pureoxygen or ozone plasma to form stoichiometric alumina at step 706.Oxidation may be followed by an appropriate anneal (not shown) tostabilize the dielectric stack. Steps 704 and 706 are preferablyrepeated until a desired thickness of alumina is obtained. Aluminum maybe deposited by atomic layer deposition (“ALD”), molecular bean epitaxy(“MBE”), electron beam evaporation, sputtering, or any other suitablemethod. This procedure should be performed in a vacuum or in a highpartial pressure of dry nitrogen gas (N₂) to ensure that no undesirableOH⁻ ions are in the environment.

[0053] Next, at 708, a passivated overlayer is deposited on thedielectric material. The passivated overlayer is preferablysilicon-rich-nitride (SRN) and is preferably deposited in a layerranging from about 0.5 to about 3.0 nm in thickness. The SRN preferablyhas a refractive index of ≧2.5. Passivated overlayer deposition can beaccomplished by a low pressure plasma enhanced chemical vapor depositionprocess with silane (SiH₄) or dichlorosilane (SiH₂Cl₂), ammonia (NH₃),and nitrogen such that the ratio of SiH₄ to NH₃, or SiH₂Cl₂ to NH₃, isapproximately ≧15. This ratio regulates the amount and distribution ofeach phase of the silicon-rich-nitride, namely the amount anddistribution of the silicon nitride insulator (Si₃N₄) and eithercrystalline or amorphous silicon (Si) particles. The ratio of SiH₂Cl₂ toNH₃ has been found to be directly proportional to the refractive indexof the resulting SRN material, as shown in FIG. 8. Thus, control of theSiH₂Cl₂/NH₃ ratio is important. For example, a SiH₂Cl₂/NH₃ ratio of 15produces a SRN material with a refractive index of approximately 2.5, avalue that ensures a K>12. As noted previously, a deposited SRN materialshould preferably have a K value similar to that of the high Kdielectric material, such that the advantages of the high K dielectricmaterial are not canceled out by a passivated overlayer with a low Kvalue.

[0054] Returning to FIG. 7, the dielectric stack may then be stabilizedby a rapid thermal anneal in nitrogen at 710. A gate and gate electrode,or top plate, are deposited at 712, depending on whether a gatedielectric stack or a storage dielectric stack is being fabricated.

[0055] If a storage capacitor is being fabricated, step 708 can beoptionally eliminated. That is, a passivated overlayer may not need tobe included in a storage dielectric stack fabricated in accordance withthe invention. Process 700 without 708 may be sufficient to achieve animproved storage capacitor stack. However, a passivated overlayer in astorage dielectric stack provides a preferably maximum achievable Kvalue and consequently higher storage capacity.

[0056] In another embodiment of a method to fabricate dielectric stacksin accordance with the invention, 704 involves depositing metal to adesired thickness and then subsequently oxidizing the entire thicknessin a controlled manner to form the desired stoichiometric dielectricmaterial. For example, aluminum may first be deposited to the desiredthickness and then oxidized to form stoichiometric alumina.

[0057]FIG. 9 shows yet another embodiment of a method to fabricateimproved dielectric stacks in accordance with the invention. In process900, 704 and 706 of process 700 are replaced by 902. At 902, adielectric material is deposited directly on a prepared substrate orbottom plate. The dielectric material if preferably alumina and may bedeposited by MBE, sputtering, or any other suitable method.

[0058] Thus it is seen that improved gate and storage dielectricsystems, and methods of their fabrication, are provided. One skilled inthe art will appreciate that the present invention can be practiced byother than the described embodiments, which are presented for purposesof illustration and not of limitation, and the present invention islimited only by the claims which follow.

I claim:
 1. A gate dielectric stack used in integrated circuit devices,said stack comprising: a substrate; a high K gate dielectric having afirst and a second surface, said second surface forming an interfacewith said substrate, said interface having a charge no greater thanabout 3e+10 fundamental charge units per cm; a gate; and a passivatedoverlayer having a first and a second surface, said second surface ofsaid passivated overlayer forming a first chemically inert interfacewith said first surface of said high K gate dielectric, said firstsurface of said passivated overlayer forming a second chemically inertinterface with said gate; wherein said K is a dielectric constant. 2.The gate dielectric stack of claim 1 wherein said substrate comprisessilicon.
 3. The gate dielectric stack of claim 1 wherein said high Kgate dielectric has a K greater than about
 10. 4. The gate dielectricstack of claim 1 wherein said high K gate dielectric comprises alumina.5. The gate dielectric stack of claim 4 wherein said high K gatedielectric has a K in the range of about 11 to about
 12. 6. The gatedielectric stack of claim 1 wherein said high K gate dielectric has a Kgreater than about
 15. 7. The gate dielectric stack of claim 1 whereinsaid high K gate dielectric comprises alumina doped with a dopant. 8.The gate dielectric stack of claim 7 wherein said dopant is selectedfrom the group consisting of silicon and a transition metal.
 9. The gatedielectric stack of claim 8 wherein said transition metal is selectedfrom the group consisting of zirconium, tungsten, hafnium, titanium, andtantalum.
 10. The gate dielectric stack of claim 1 wherein said gatecomprises material selected from the group consisting of degenerateheavily doped polysilicon and metal.
 11. The gate dielectric stack ofclaim 1 wherein said passivated overlayer comprisessilicon-rich-nitride.
 12. The gate dielectric stack of claim 11 whereinsaid silicon-rich-nitride has a refractive index of greater than about2.5.
 13. The gate dielectric stack of claim 11 wherein said passivatedoverlayer has a thickness in the range of about 0.5 to about 3 nm.
 14. Astorage dielectric stack used in integrated circuit devices, said stackcomprising: a first plate; a high K storage dielectric having a firstand a second surface, said second surface forming an interface with saidfirst plate, said interface having a charge no greater than about 3e+10fundamental charge units per cm²; a second plate; and a passivatedoverlayer having a first and a second surface, said second surface ofsaid passivated overlayer forming a first chemically inert interfacewith said first surface of said high K storage dielectric, said firstsurface of said passivated overlayer forming a second chemically inertinterface with said second plate; wherein said K is a dielectricconstant.
 15. The storage dielectric stack of claim 14 wherein saidfirst plate comprises degenerate heavily doped silicon.
 16. The storagedielectric stack of claim 14 wherein said high K storage dielectric hasa K greater than about
 10. 17. The storage dielectric stack of claim 14wherein said high K storage dielectric comprises alumina.
 18. Thestorage dielectric stack of claim 17 wherein said high K storagedielectric has a K in the range of about 11 to about
 12. 19. The storagedielectric stack of claim 14 wherein said high K storage dielectric hasa K greater than about
 15. 20. The storage dielectric stack of claim 14wherein said high K storage dielectric comprises alumina doped with adopant.
 21. The storage dielectric stack of claim 20 wherein said dopantis selected from the group consisting of silicon and a transition metal.22. The storage dielectric stack of claim 21 wherein said transitionmetal is selected from the group consisting of zirconium, tungsten,hafnium, titanium, and tantalum.
 23. The storage dielectric stack ofclaim 14 wherein said second plate comprises material selected from thegroup consisting of doped polysilicon and metal.
 24. The storagedielectric stack of claim 14 wherein said passivated overlayer comprisessilicon-rich-nitride.
 25. The storage dielectric stack of claim 24wherein said silicon-rich-nitride has a refractive index of greater thanabout 2.5.
 26. The storage dielectric stack of claim 24 wherein saidpassivated overlayer has a thickness in the range of about 0.5 to about3 nm.
 27. A gate dielectric stack used in integrated circuit devices,said stack comprising: a substrate; an alumina gate dielectric having afirst and a second surface, said second surface forming an interfacewith the substrate; a gate; and a silicon-rich-nitride overlayer havinga first and a second surface, said second surface of saidsilicon-rich-nitride overlayer forming a first chemically inertinterface with said first surface of said alumina gate dielectric, saidfirst surface of said silicon-rich-nitride overlayer forming a secondchemically inert interface with said gate.
 28. The gate dielectric stackof claim 27 wherein said substrate comprises silicon.
 29. The gatedielectric stack of claim 27 wherein said alumina gate dielectric has aK in the range of about 11 to about 12 and said K is a dielectricconstant.
 30. The gate dielectric stack of claim 27 wherein said aluminagate dielectric is doped with a dopant.
 31. The gate dielectric stack ofclaim 30 wherein said dopant is selected from the group consisting ofsilicon and a transition metal.
 32. The gate dielectric stack of claim27 wherein said silicon-rich-nitride overlayer has a refractive index ofgreater than about 2.5.
 33. The gate dielectric stack of claim 27wherein said silicon-rich-nitride overlayer has a thickness in the rangeof about 0.5 to about 3 nm.
 34. The gate dielectric stack of claim 27wherein said interface has a charge no greater than about 3e+10fundamental charge units per cm².
 35. A storage dielectric stack used inintegrated circuit devices, said stack comprising: a first plate; analumina storage dielectric having a first and a second surface, saidsecond surface forming an interface with said first plate; a secondplate; and a silicon-rich-nitride overlayer having a first and a secondsurface, said second surface of said silicon-rich-nitride overlayerforming a first chemically inert interface with said first surface ofsaid alumina storage dielectric, said first surface of saidsilicon-rich-nitride overlayer forming a second chemically inertinterface with said second plate.
 36. The storage dielectric stack ofclaim 35 wherein said first plate comprises degenerate heavily dopedsilicon.
 37. The storage dielectric stack of claim 35 wherein saidalumina storage dielectric has a K in the range of about 11 to about 12and said K is a dielectric constant.
 38. The storage dielectric stack ofclaim 35 wherein said alumina storage dielectric is doped with a dopant.39. The storage dielectric stack of claim 38 wherein said dopant isselected from the group consisting of silicon and a transition metal.40. The storage dielectric stack of claim 35 wherein saidsilicon-rich-nitride overlayer layer has a refractive index of greaterthan about 2.5.
 41. The storage dielectric stack of claim 35 whereinsaid silicon-rich-nitride overlayer has a thickness in the range ofabout 0.5 to about 3 nm.
 42. The storage dielectric stack of claim 35wherein said interface has a charge no greater than about 3e+10fundamental charge units per cm².
 43. A gate dielectric stack used inintegrated circuit devices, said stack comprising: a substrate; analumina gate dielectric having a first and a second surface, said secondsurface forming an interface with said substrate, said alumina gatedielectric having a K in the range of about 11 to about 12, said K beinga dielectric constant, said interface having a charge no greater thanabout 3e+10 fundamental charge units per cm²; a gate; and asilicon-rich-nitride overlayer having a first and a second surface, saidsecond surface of said silicon-rich-nitride overlayer forming a firstchemically inert interface with said first surface of said alumina gatedielectric, said first surface of said silicon-rich-nitride overlayerforming a second chemically inert interface with said gate, saidsilicon-rich-nitride overlayer having a refractive index greater than orequal to about 2.5, said silicon-rich-nitride layer having a thicknessin the range of about 0.5 to about 3 nm.
 44. The gate dielectric stackof claim 43 wherein said alumina gate dielectric is doped with a dopant.45. The gate dielectric stack of claim 44 wherein said dopant isselected from the group consisting of silicon and a transition metal.46. A storage dielectric stack used in integrated circuits, said stackcomprising: a first plate; an alumina storage dielectric having a firstand a second surface, said second surface forming an interface with saidfirst plate, said interface having a charge no greater than about 3e+10fundamental charge units per cm²; a second plate; and asilicon-rich-nitride overlayer having a first and a second surface, saidsecond surface of said silicon-rich-nitride overlayer forming a firstchemically inert interface with said first surface of said aluminastorage dielectric, said first surface of said silicon-rich-nitrideoverlayer forming a second chemically inert interface with said secondplate, said silicon-rich-nitride overlayer having a refractive indexgreater than or equal to about 2.5, said silicon-rich-nitride layerhaving a thickness in the range of about 0.5 to about 3 nm.
 47. Thestorage dielectric stack of claim 46 wherein said alumina storagedielectric is doped with a dopant.
 48. The storage dielectric stack ofclaim 47 wherein said dopant is selected from the group consisting ofsilicon and a transition metal.
 49. A method of fabricating a gatedielectric stack for a field effect transistor, said method comprising:removing native Si_(x)O_(y)H_(z) from a region of a substrate;depositing on said region a layer of metal that forms a high Kdielectric material when oxidized; oxidizing said layer to form saidhigh K dielectric material; depositing a passivated overlayer on saidlayer; depositing a gate on said passivated overlayer; and depositing agate electrode on said gate; wherein said K is a dielectric constant.50. The method of claim 49 further comprising doping said high Kdielectric material.
 51. The method of claim 50 wherein said dopingcomprises doping said high K dielectric material with a materialselected from the group consisting of silicon and a transition metal.52. The method of claim 51 wherein said transition metal is selectedfrom the group consisting of zirconium, tungsten, hafnium, titanium, andtantalum.
 53. The method of claim 49 further comprising annealing saidgate dielectric stack by rapid thermal annealing to stabilize saidstack.
 54. The method of claim 53 wherein said annealing said gatedielectric stack is performed immediately following said depositing apassivated overlayer.
 55. The method of claim 53 wherein said annealingsaid gate dielectric stack is performed immediately following saidoxidizing.
 56. The method of claim 49 wherein said removing nativeSi_(x)O_(y)H_(z) comprises: inserting said substrate into a vacuumchamber; controllably introducing hydrofluoric acid vapor in an ultrapure nitrogen bleed-in; and maintaining a vacuum in said vacuum chamberof less than about 10⁻⁶ torr during said introducing.
 57. The method ofclaim 49 wherein said depositing a layer of metal comprises depositing alayer of metal by a process selected from the group consisting of atomiclayer deposition, molecular beam epitaxy, electron beam evaporation, andsputtering.
 58. The method of claim 49 wherein said depositing a layerof metal comprises depositing a layer of aluminum.
 59. The method ofclaim 49 wherein said depositing a layer of metal comprises depositing alayer of aluminum having a thickness of less than about 3 nm.
 60. Themethod of claim 49 wherein said depositing a passivated overlayercomprises depositing a passivated overlayer of silicon-rich-nitride by alow pressure plasma enhanced chemical vapor deposition with SiH₄ orSiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃is no less than about
 15. 61. The method of claim 49 wherein saiddepositing a passivated overlayer comprises depositing an overlayer ofsilicon-rich-nitride having a refractive index greater than about 2.5.62. The method of claim 49 wherein said depositing a passivatedoverlayer comprises depositing an overlayer of silicon-rich-nitridehaving a thickness in the range of about 0.5 to about 3 nm.
 63. A methodof fabricating a storage dielectric stack for an integrated circuitdevice, said method comprising: removing native Si_(x)O_(y)H_(z) from aregion of a first plate; depositing on said region a layer of metal thatforms a high K dielectric material when oxidized; oxidizing said layerto form said high K dielectric material; depositing a passivatedoverlayer on said layer; and depositing a second plate on saidpassivated overlayer; wherein said K is a dielectric constant.
 64. Themethod of claim 63 further comprising doping said high K dielectricmaterial.
 65. The method of claim 64 wherein said doping comprisesdoping said high K dielectric material with a material selected from thegroup consisting of silicon and transition metal.
 66. The method ofclaim 65 wherein said transition metal is selected from the groupconsisting of zirconium, tungsten, hafnium, titanium, and tantalum. 67.The method of claim 63 further comprising annealing said storagedielectric stack by rapid thermal annealing to stabilize said stack. 68.The method of claim 67 wherein said annealing said gate dielectric stackis performed immediately following said depositing a passivatedoverlayer.
 69. The method of claim 67 wherein said annealing said gatedielectric stack is performed immediately following said oxidizing. 70.The method of claim 63 wherein said removing native Si_(x)O_(y)H_(z)comprises: inserting said first plate into a vacuum chamber;controllably introducing hydrofluoric acid vapor in an ultra purenitrogen bleed-in; and maintaining a vacuum in said vacuum chamber ofless than about 10⁻⁶ torr during said introducing.
 71. The method ofclaim 63 wherein said depositing a layer of metal comprises depositing alayer of metal by a process selected from the group consisting of atomiclayer deposition, molecular beam epitaxy, electron beam evaporation, andsputtering.
 72. The method of claim 63 wherein said depositing a layerof metal comprises depositing a layer of aluminum.
 73. The method ofclaim 63 wherein said depositing a layer of metal comprises depositing alayer of aluminum having a thickness of less than about 3 nm.
 74. Themethod of claim 63 wherein said depositing a passivated overlayercomprises depositing a passivated overlayer of silicon-rich-nitride by alow pressure plasma enhanced chemical vapor deposition with SiH₄ orSiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃is no less than about
 15. 75. The method of claim 63 wherein saiddepositing a passivated overlayer comprises depositing an overlayer ofsilicon-rich-nitride having a refractive index not less than about 2.5.76. The method of claim 63 wherein said depositing a passivatedoverlayer comprises depositing an overlayer of silicon-rich-nitridehaving a thickness in the range of about 0.5 to about 3 nm.
 77. A methodof fabricating a gate dielectric stack for a field effect transistor,said method comprising: removing native Si_(x)O_(y)H_(z) from a regionof a substrate; depositing a layer of aluminum having a thickness ofless than about 3 nm on said region; oxidizing said layer of aluminum toform a layer of alumina; depositing a passivated overlayer ofsilicon-rich-nitride on said layer of alumina by a low pressure plasmaenhanced chemical vapor deposition process, said passivated overlayerhaving a thickness of about 0.5 to about 3 nm, said passivated overlayerhaving a refractive index no less than about 2.5, said low pressurechemical vapor deposition process using SiH₄ or SiH₂Cl₂, NH₃, andnitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃ is no less thanabout 15; depositing a gate on said passivated overlayer; and depositinga gate electrode on said gate.
 78. The method of claim 77 furthercomprising annealing said gate dielectric stack by rapid thermalannealing to stabilize said stack.
 79. The method of claim 78 whereinsaid annealing said gate dielectric stack is performed immediatelyfollowing said depositing a passivated overlayer.
 80. The method ofclaim 78 wherein said annealing said gate dielectric stack is performedimmediately following said oxidizing.
 81. The method of claim 77 whereinsaid removing native Si_(x)O_(y)H_(z) comprises: inserting saidsubstrate into a vacuum chamber; controllably introducing hydrofluoricacid vapor in an ultra pure nitrogen bleed-in; and maintaining a vacuumin said vacuum chamber of less than about 10⁻⁶ torr during saidintroducing.
 82. A method of fabricating a storage dielectric stack foran integrated circuit device, said method comprising: removing nativeSi_(x)O_(y)H_(z) from a region of a first plate; depositing a layer ofaluminum having a thickness of less than about 3 nm on said region;oxidizing said layer of aluminum to form a layer of alumina; depositinga passivated overlayer of silicon-rich-nitride on said layer of aluminaby a low pressure plasma enhanced chemical vapor deposition process,said passivated overlayer having a thickness of about 0.5 to about 3 nm,said passivated overlayer having a refractive index no less than about2.5, said low pressure chemical vapor deposition process using SiH₄ orSiH₂Cl₂, NH₃, and nitrogen such that the ratio of SiH₄ or SiH₂Cl₂ to NH₃is no less than about 15; and depositing a second plate on saidpassivated overlayer.
 83. The method of claim 82 further comprisingannealing said storage dielectric stack by rapid thermal annealing tostabilize the stack.
 84. The method of claim 83 wherein said annealingsaid gate dielectric stack is performed immediately following saiddepositing a passivated overlayer.
 85. The method of claim 83 whereinsaid annealing said gate dielectric stack is performed immediatelyfollowing said oxidizing.
 86. The method of claim 82 wherein saidremoving native Si_(x)O_(y)H_(z) comprises: inserting said first plateinto a vacuum chamber; controllably introducing hydrofluoric acid vaporin an ultra pure nitrogen bleed-in; and maintaining a vacuum in saidvacuum chamber of less than about 10⁻⁶ torr during said introducing.